Prefered syntax for verilog module declaration -

i relatively new fpgas, , looking guidance modern best practice regarding declaration of modules in verilog.

i have seen 2 ways of declaring module in verilog. first reminds me of traditional c, such examples on wikipedia:

module toplevel(clock,reset);     input clock;     input reset;      /* snip */ endmodule 

whereas alternative syntax has input/output specifier part of argument list, not dissimilar vhdl, in this example:

module fadder(     input a,         //data in     input b,         //data in b     input cin,       //carry in     output sum_out,  //sum output     output c_out     //carry output );  /* snip */ endmodule 

for newly written verilog code, syntax preferred? "preferred", in instance, means written in standard or related material (either explicitly written, or implicitly examples given in standard), or written in well-regarded style guide. question isn't asking personal preference!

the second syntax form indented replace first syntax form. if @ 1364-2001 verlog lrm, current 1800-2012 systemverilog lrm, notice examples of module declarations use second form. first form there legacy, unfortunately, has taken longer expected textbooks , course material switch over.

the key benefit of newer (or ansi-style) syntax have declare port name in 1 place. older syntax, had declare port name 3 times; once positional ordering, time port direction, , if port needed other wire, third time declare data type.