verilog - How does clock gating in RTL design work? -

i'm trying understand how clock gating works in rtl design.

i've example wave here:

description:

1st signal gated_clock 2nd signal clock_enable 3rd signal ungated_clock 

so there 3 cycles in wave (let's cycle 0,1,2). in cycle 0, clock_enable low , gated_clock turned off. in cycle 1 clock_enable goes high , in next cycle (cycle 2) gated_clock turns on.

now, during simulation see cases incoming data received @ cycle 1 being registered module gated clock (using gated_clock). it's kinda odd me , don't quite understand how it's possible.

the logic this:

always_ff @(posedge gated_clock, negedge reset) begin    if (~reset) begin       some_val <= 1'b0;    end else begin       if (in_valid==1'b1 && in_ready==1'b1) begin          some_val <= in_val;       end else begin          some_val <= 1'b0;       end    end end 

so i'm seeing if in_valid , in_ready high in cycle 1 some_val register incoming in_val data , it'll available in cycle 2. in cycle 1, gated_clock zero. how did in_val sampled here? understand, posedge gated_clock must 1 if want flop in_val in cycle 1 .

i might missing core circuit level digital design concept. i'll appreicate help.

updated wave:

1st signal gated_clock 2nd signal clock_enable 3rd signal ungated_clock 4th signal in_valid 5th signal in_ready 6th signal in_val 7th signal some_val 

so here see @ cycle 0, gated_clock off in_val , in_ready high. input data in_val high. in next cycle some_val goes high. looks in_val captured in cycle 0 though gated_clock off.

it's possible there glitch on gated clock that's not showing on waveform. you'll need @ user manual of tool you're using find out how record , display glitches. might see logic gating clock. clock_enable assigned using nba (<=)?